Full-Stack Design and Toolchain Exploration of a Scalable and Flexible Hardware Accelerator for Deep Learning Based on RISC-V and Digital In-Memory Computing
This work explores novel solutions to integrate and fully exploit the potential of Digital In-Memory Computing (DIMC) within a RISC-V-based system. The main objective is to design a scalable hardware architecture that harnesses the DIMC paradigm to accelerate a wide range of deep learning workloads through software-controlled execution. By tightly coupling the accelerator with the RISC-V core, the execution flow is governed entirely by instructions, allowing for multiple degrees of freedom in managing data movement and computation. This flexibility is a defining feature, enabling the hardware to adapt to diverse application domains. Additionally, the modularity of the design ensures scalability, making it suitable for deployment in both low-power edge scenarios and high-performance computing systems, depending on the number and configuration of instantiated modules.
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