High-Speed Pipeline-SAR Hybrid A/D Converters
The growing demand for higher data rates, low latency, and increased connectivity has driven the development of advanced wireless standards such as 5G and Wi-Fi 7 (IEEE 802.11be). These technologies require wide channel bandwidths, high-order modulation, and massive MIMO, setting stringent demands on radio transceivers. Analog-to-digital converters (ADCs) are critical, as they must achieve gigahertz sampling rates with high resolution and linearity. This thesis presents the design of a digitally assisted time-interleaved (TI) pipeline-SAR ADC, offering improved speed and energy efficiency compared to conventional SAR and 1b-pipelined architectures. The implemented 2-GS/s, 4×-TI pipeline-SAR ADC in 28-nm CMOS achieves 10-bit equivalent resolution and a spurious-free dynamic range (SFDR) above 75 dBc, demonstrating its potential for next-generation wireless transceivers.
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