Giga-sample-per-second hybrid analog-to-digital converters in highly-scaled CMOS technology
Newly developed wireless standards are meant to achieve data rates in the order of several tens of Gb/s, latency below 100 us, and high power efficiency. These requirements make the design of transceivers very challenging. One of the most critical components is analog-to-digital converters (ADCs), whose purpose is to digitalize the information to be processed by the digital signal processor (DSP). To fulfill the requirements, the ADC must operate at a rate of a few Gs/s with around 10 equivalent bits and power below 100 mW. The architecture of choice is a hybrid SAR-pipe with time-interleaved channels to realize both an efficient and fast converter. The circuit will be implemented in a 28nm planar CMOS technology.
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