Modern RISC-V system-on-chip architectures for data-center applications
This research aims to develop a methodology for the design of RISC-V-based computing platforms optimized for HPC and data-center scenarios, in which data access is a key bottleneck. The research will focus on optimizing the uncore components of the SoC and it will define semi-automatic methodologies for optimizing PPA metrics and produce a co-simulation tool that enables RTL-level simulation of the elements under investigation, while simulating the rest of the system at cycle-accurate level.
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