HARDWARE SUPPORT FOR SECURE RISC-V MICROPROCESSORS

Advisor: Prof. Luca Maria Cassano

Keywords: Integrated circuits, System-on-Chip (SoC), Intelligent Security Checkers (ISCs)

Computing platforms for modern embedded systems, e.g., automotive systems or next generation satellites, are required to be flexible, high-performance and low-cost. To achieve these requirements, integrated circuits are produced following a globally distributed design flow: the System-on-Chip (SoC) will integrate modules designed inhouse with other modules coming from third party entities, either in the form of Third-Party IP cores (3PIPs) or in the form of Commercial Off-the-Shelf (COTS) components. Moreover, the final fabrication of the silicon device will rely on outsourced foundries. While ensuring highperformance and reduced cost, such globalized design process exposes the obtained system to several security threats both at design time and at runtime. In particular, purchased IP cores may contain unwanted functionalities or the final produced integrated circuit may be maliciously modified. Such stealthy unwanted functionalities are known as Hardware Trojan Horses (HTHs).The goal of the PhD is to the system Intelligent Security Checkers (ISCs) meant for monitoring the activity carried out by the microprocessor and to detect at runtime the activation of HTHs and Transient Execution Attacks, e.g., Spectre and Meltdown. As a beneficial additional side-effect, such ISCs would also allow to detect anomalous behaviors due to random faults (e.g. Soft Errors in memories, SEUs inregisters) instead of malicious attacks. Of course, it is mandatory for the introduced security checker not to interfere with the nominal functioning of the system, i.e., not to introduce working frequency slow-down, and to bring the smallest possible silicon area and power consumption overhead.

• Computer Science and Engineering
• Company-sponsored

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